A general function ASIC device consists of logic functions such as combinatorial circuits, latches and registers, memory blocks, input/output buffers, and other custom functions. In the prior art, logic functions are derived from a configurable logic block (CLB) in the same manner as these functions are configured in Field Programmable Gate Array (FPGA) devices, except interconnections are made in a semiconductor process line with reduced masking steps. One example of such a CLB is shown in FIG. 1. It consists of a 4:1 multiplexer and a DFF with scan. Two input Boolean logic functions are generated from the 4:1 multiplexer. Different combinatorial functions are generated from the 4:1 multiplexer by connecting inputs D0 to D3 to a power supply (VDD) or ground (GND) while real signal inputs are applied to input In1 and input In2. A truth table of a two way NAND function configured with a CLB in the prior art is also given in FIG. 1. Any delay and power dissipation of these logic functions are caused by the multiplexer and not the actual logic functions. Configured logic functions from CLBs use many more circuits to implement a logic function compared with the method of achieving logic functions in the conventional Gate Array or Standard Cell ASIC design methodologies. This results in lower performance and/or higher power dissipation of the ASIC devices. In the prior art, structured ASIC design requires a special EDA (Event Driven Architecture) software system specially tailored to a designer's methodology.
The art is therefore in need of a less complex and more flexible process to manufacture ASIC devices.